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Research PublicationMulti-scale modeling of nano scale phenomenon using CUDA based HPC setup
Authors
KeywordsHPC(High Performance Computing), Nano Simulation, Multi-Scale Modeling, CUDA AbstractThe essence of High performance computing (HPC) in the field of computation Nanotechnology and problems encountered by HPC arrangement in applying HPC to Nano-enabled calculations have been presented in the paper. A proposal to optimize computations in an HPC setup has been formulated to make Nanotechnology computations more effective and realistic on a CUDA based framework. Results and findings in the expected setup and the computation complexities that will be needed in its implementation have been suggested with an algorithm to take advantage of inbuilt powerful parallelization capabilities of GPU making large scale simulation possible. Implementation of CUDA in certain complex techniques in Nanotechnology is presented with a significant improvement in performance as compared to the last work which was implemented using distributive computing toolbox in MATLAB. We have discussed about the problems that exist and how we can optimize the computations in a HPC setup and how we can make use of computational power of GPU to make Nanotechnology computations more effective and realistic. A description of the progress in this area of research, future works and a probable extension is proposed. Publication DetailsPublished inThe First South Central Asian Himalayas Regional IEEE/IFIP International Conference on INTERNET AH – ICI 2009
Also published in IEEE Xplore
Manuscript receivedAugust 15, 2009. IEEE Catalog NumberCFP0931H-CDR International Standard Book Number (ISBN)978-1-4244-4569-1 Library of Congress2009903977 Digital Object Identifier (DOI)10.1109/AHICI.2009.5340321 Conference DetailsConference Name
The First South Central Asian Himalayas Regional IEEE/IFIP International Conference on INTERNET AH – ICI 2009
Organizer
Ministry of Environment Science and Technology
National Information Technology Center, Nepal
Technical Sponsor
Institute of Electrical and Electronics Engineers (IEEE)
VenuHyatt Regency Kathmandu, KATHMUNDU, NEPAL Conference Date3rd - 5th November 2009 Related LinksVisit Conference Website Online References
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Page Last Updated Friday 27 November 2009 |
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