Research Publication

Reliability modeling of MEMS devices on CUDA based HPC setup

Authors

Rohit Pathak

He is with the Computer Science Department, Acropolis Institute of Technology & Research, Indore, M.P., India (e-mail: rohitpathak@ieee.org)

Satyadhar Joshi

He is with the Electronics & Electricals Dept., Shri Vaishnav Institute of Technology & Science, Indore, M.P., India (e-mail: satyadhar_joshi@yahoo.com)

Keywords

HPC(High Performance Computing), Nano Simulation, Multi-Scale Modeling, Reliability, Compute Unified Device Architecture (CUDA)

Abstract

In this paper we have reviewed the development in CUDA and the implementation of various distribution that exists in the reliability for MEMS based devices on a CUDA setup. The various distributions can be highly optimized so that the system can be simulated highly on CUDA. We have shown the type of distribution may vary from exponential to binomial to other that are being proposed recently. The Reliability modeling codes to calculate reliability function, failure rate function, Mean time to failure (MTTF) and Mean Residual time (MRT) are proposed for MEMS technology for these specific calculations needs to be performed for which CUDA plays a very important role. It is observed that High Performance Computing (HPC) can be used to optimize reliability calculation and help to accelerate research in reliability of MEMS. The three key abstractions of CUDA i.e. hierarchy of thread groups, shared memories, and barrier synchronization are exposed as a set of extensions to C language, which provides fine-grained data parallelism and thread parallelism, nested within coarse-grained data parallelism and task parallelism. The key is division of the computations of Reliability analysis into crude sub-problems that can be solved parallely in isolation independently, and then into finer pieces that can be executed in parallel with mutual cooperation among them. Allowing threads to solve each sub-problem cooperatively, this division of problem preserves expressivity of language. Each sub-problem is thus scheduled to be solved on any of the available processor cores allowing transparent scalability. Thus computations of Reliability analysis can be performed by using a compiled CUDA program that can execute on any number of GPU cores. During the programming we need not know the exact configuration and thus only the runtime system needs to know the physical processor count.

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Publication Details

Published in

The First South Central Asian Himalayas Regional IEEE/IFIP International Conference on INTERNET AH – ICI 2009

Also published in IEEE Xplore

Manuscript received

August 15, 2009.

IEEE Catalog Number

CFP0931H-CDR

International Standard Book Number (ISBN)

978-1-4244-4569-1

Library of Congress

2009903977

Digital Object Identifier (DOI)

10.1109/AHICI.2009.5340289

Conference Details

Conference Name

The First South Central Asian Himalayas Regional IEEE/IFIP International Conference on INTERNET AH – ICI 2009

Organizer

Ministry of Environment Science and Technology National Information Technology Center, Nepal

Institute of Engineering IOE, Nepal

Nepal College of Information Technology, Nepal

Nepal Engineering College, Nepal

IEEE Communications Society

Technical Sponsor

Institute of Electrical and Electronics Engineers (IEEE)

Venu

Hyatt Regency Kathmandu, KATHMUNDU, NEPAL

Conference Date

3rd - 5th November 2009

Related Links

Visit Conference Website Online

References

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